The present invention relates to a semiconductor structure having a strained crystalline layer formed on a single crystal substrate or on an insulator and further to a method for fabricating such a semiconductor structure.
Strained, thin semiconductor layers, such as silicon layers, have enhanced electron and hole mobility characteristics which are advantageous for improving speed or decreasing power requirements of electronic devices. Because their use can lead to high performance devices having high speed and low power consumption, such layers are of interest in nearly all parts of microelectronics.
Strain in silicon layers can be induced, for instance, by growing a thin silicon layer on a relaxed SiGe layer with a high concentration of germanium. Because silicon is the smaller atom, the stress between silicon and such a SiGe layer increases gradually with increasing Ge concentration, and more favorable strain values can be achieved when the germanium concentration of the SiGe layer is as large as possible.
U.S. Published Application No. 2002/0084000 A1 discloses a method and a semiconductor structure for growing a GeSi layer with a gradually increasing germanium content on a silicon substrate up to a germanium content of about 50%. Increasing germanium content of the graded GeSi layer causes cracks and a high number of threading dislocations to occur in the layer. In order to remove a cross-hatch pattern on the surface of the GeSi layer, a surface planarization step such as a Chemical Mechanical Polishing is applied to the GeSi surface. The planarization step prevents the continued roughening of the surface and leads to dislocation blocking as grading continues, and the germanium content of the GeSi is further increased until a pure Ge layer results on the top of the structure.
International Publication No. WO 02/15244 A2 describes a method and a semiconductor structure that provides a SiGe buffer layer that serves as a seed layer for a strained silicon film. A SiGe layer is deposited on a single crystal silicon wafer, wherein the germanium concentration is gradually increased up to 25% germanium. Then, a relaxed SiGe cap layer is deposited, having a final Ge composition of 25%. The process of growing a relaxed SiGe layer is very complex. The growth generates a very high density of misfit dislocations and a cross-hatch pattern of the SiGe layer. Furthermore, the above method is limited to a germanium content below 40% when a crystal defect density below 104 cm−2 is targeted.
Strained semiconductor layers can also be effectively used if they are transferred on an insulator layer, resulting in a SOI (silicon-on-insulator)-type structure, whose benefits are commonly known in microelectronics and micromechanics.
A publication by Cheng et al. at the 2001 IEEE International SOI Conference called “SiGe-on-Insulator (SGOI): Substrate Preparation and MOSFET Fabrication for Electron Mobility Evaluation” describes a method for fabricating a SiGe-on-insulator structure. A graded SiGe layer was grown on a single crystalline silicon donor wafer. During SiGe growth, the germanium content was gradually increased until a germanium concentration of about 25% was reached. A relaxed SiGe layer was then grown on the graded SiGe layer, and hydrogen ions were implanted into the relaxed SiGe layer, forming a weakened zone in the relaxed SiGe layer. The implanted structure was then bonded with an oxidized silicon wafer. After annealing, the bonded structure was split into two parts along the weakened zone resulting in the SiGe-on-insulator structure and a residual structure. A strained silicon layer was then grown on the SiGe layer resulting in a Si-on-SiGe-on-insulator structure.
This resulting structure, however, has a critical disadvantage in that the strain of the strained silicon layer on top of the SiGe layer cannot be increased to a value of commercial importance. This is due to the limited germanium content of the SiGe layer which cannot be increased over 25% without risking formation of a high dislocation density in the SiGe layer, which considerably influences the electronic characteristics of the strained silicon layer.
The present invention addresses these problems of the prior art, by providing a commercially useful high-strained silicon layer with a low defect density on a single crystal substrate as well as on an insulator.